The present invention relates generally to multiplexed communication systems, and more particularly to multiple access, carrier sense systems and methods, in which signal synchronization is accomplished by detecting changes of state of the communication data signal.
In multiplexed communication systems, some method of maintaining signal synchronization among the interconnected nodes is generally required. Various synchronization systems and methods are known, including utilizing a separate clocking signal; embedding a periodic synchronization symbol within the data stream; and synchronizing on each bit in the data stream.
Multiple access communication systems allow more than one node to transmit information on a shared communication channel or bus. In such systems, means may be provided to avoid simultaneous transmissions, including assignment of unique time slots to each node in which the time slots are measured from a synchronizing symbol; bus control via a bus master; and non-destructive arbitration.
With reference to FIG. 1, a data communication system may include bus 10 for connecting plural nodes 12 to plural microprocessors 14. The nodes 12 may include one or more microprocessors 14 and each microprocessor and/or node may include a circuit 16 for interfacing with the bus. The interface circuit 16 may include control logic 18, timing generator 20, a CRC generator 22, and an encoder/decoder 24 for generating data signals that match system specifications and for decoding signals received from the bus. A separate transceiver 26 may be provided.
In systems that synchronize on each bit in the data stream and use non-destructive arbitration, dominant and recessive symbols (bits) may be defined so that when multiple nodes transmit simultaneously, a recessive bit will appear on the bus only when all transmitting nodes simultaneously produce a recessive bit. In the event that a node transmits a dominant bit while one or more other nodes transmit recessive bits, the dominant bit will be transmitted on the bus. During arbitration, all nodes must "sense" the bit type which appears on the bus. If a node which is attempting to transmit a recessive bit detects a dominant bit on the bus that node must cease transmitting on the bus. Synchronization on bit boundaries by multiple nodes requires that each transmitting node initiate generation of each data bit at the end of the previous data bit as detected on the bus.
In such prior art systems, signal synchronization may be accomplished by detecting changes of state of the signal (a change of state being denoted a "transition"), and synchronization may be lost if a node is damaged so that it can no longer sense transitions on the bus. The damaged node will not be able to detect when one bit has ended and transmission of the next bit should commence. As a minimum this renders the node incapable of transmitting, and in certain systems can cause communications on the bus to be inhibited. In all cases it is desirable that such a fault be detected.
Messages are typically sent along the bus (single wire, or multiple wire) and at any given time the bus can be in either of two states: active (high) or passive (low). By way of example, a standard system (SAE Recommended Practice J1850, Class B Data Communication Network Interface, Sept. 1, 1993) establishes requirements for communications on a multiplexed bus. Multiple nodes may be connected to the bus and the bus is high if any one (or more) of the nodes is generating an active output, and the bus is low if no nodes are generating active outputs. The bus is in a passive state when at rest.
A message begins when the bus is first driven high, and each succeeding state transition (high to low, or low to high) transfers one bit of information until the message is complete. The definition of each bit is dependent on its state (high or low) and its duration, and such messages are appropriately described as Variable Pulse Width (VPW). As illustrated in FIG. 2, each message spans a frame, and begins with an active start of frame (SOF) bit, includes bytes of address information and data, and ends with a passive end of frame (EOF) bit. Messages are transmitted with the most significant bit (MSB) first. The duration of each bit is measured as the time between successive transitions, and there is one bit per transition. For the J1850 standard, durations of bits (TV values) and bit definitions have been established and are shown in Tables 1 and 2 below.
TABLE 1 ______________________________________ J1850 Timing Pulse Value (TV) Definitions DURATION (ALL TIMES IN .mu.s) TV ID MINIMM NOMINAL MAXIMUM ______________________________________ Illegal 0 N/A .ltoreq.34 TV1 &gt;34 64 .ltoreq.96 TV2 &gt;96 128 .ltoreq.163 TV3 &gt;163 200 .ltoreq.239 TV4 &gt;239 280 N/A TV5 &gt;239 300 N/A TV6 &gt;280 300 N/A ______________________________________
TABLE 2 ______________________________________ Bit Definitions BIT DEFINITION ______________________________________ 0 Data Passive TV1 or Active TV2 1 Data Active TVI or Passive TV2 SOF (Start of Frame) Active TV3 EOD (End of Data) Passive TV3 EOF (End of Frame) Passive TV4 IFS (Inter-Frame Separation) Passive TV6 IDLE (Idle Bus) Passive &gt;TV6 Nominal NB (Normalization Bit) Active TV1 or Active TV2 BRK (Break) Active TV5 ______________________________________
As is obvious, operation of such systems depends on accurate timing of bit duration, and to this end the encoder/decoders 24 of such systems may include binary counters that provide a count of the number of clock signals received since the last transition so that the system is re-synchronized on each bit. In the J1850 example above, a counter may count the number of microseconds from the last transition, the count between bit transitions thus being indicative of the bit duration (e.g., a count of 64 would indicate a TV1 bit).
Binary counters are well known and need not be discussed in detail for an understanding of the present invention. A binary counter provides a count signal indicating the number of clock signals received at the counter, and typically includes N serially connected stages, each for providing an output indicating its state has been changed. The clock signal may be provided synchronously, to all stages simultaneously so that counter output is always correct, or asynchronously, to the first stage so that the signal cascades through the stages and the counter output is only correct when the signal has cascaded to the last stage. Outputs from each stage are provided to a decoder array that provides a count signal.
Prior art systems typically include two counters, one for timing the duration of the outgoing bit so that it has the appropriate definition, and one for timing when the transmitted bit is sensed on the bus. If the transmitted bit is not sensed on the bus within a predetermined time period, a fault may exist in either the transmit or sense path. If the bit is received as expected (that is, the same state and bit duration, within specified limits), there is no fault and normal operation continues. As will be appreciated, the second counter adds cost and increases device size (e.g., chip area).
Accordingly, it is an object of the present invention to provide a novel method and device for timing the duration of bits in a data communication system that obviates the problems of the prior art.
It is another object of the present invention to provide a novel method and device for timing the duration of transmitted and received bits in a data communication system in which a single counter/decoder serves multiple purposes; timing received bit duration during normal operation, timing transmitted bit duration when transmitting, and/or timing reflections of bits from the bus to determine whether a fault may exist when transmitting.
It is yet another object of the present invention to provide a novel method and device for timing the duration of transmitted bits in a data communication system in which the counter/decoder starts a time count upon receipt of the reflection from the bus of the transmitted bit transition, and indicates that the next transition is to be sent at the end of a time count defined by the bit duration minus a bit travel time that is the time from transmission of a bit transition to receipt of the transmitted bit transition.
It is still another object of the present invention to provide a novel method and device for timing the duration of transmitted bits in a data communication system in which the counter/decoder starts a time count if the reflected bit transition is received, and indicates a fault if the reflected bit transition has not been received for a period of time longer than the bit travel time.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.